1. Field of the Invention
This invention relates to microprocessor systems. In particular, the invention relates to use of field-effect transistor (FET) switches for large memory arrays.
2. Description of Related Art
High performance microprocessor systems typically involve a large number of high speed memories. Interfacing these memories to the processor typically includes connecting all the data lines of the memory devices to the processor's data bus lines. Connecting a large number of data lines to the processor's data bus creates a number of problems. The major problem is the high capacitive load caused by a large number of data lines tied together. Four dynamic random access memory (DRAM) modules can have up to 80 picofarads (pf) on the data lines typically. A large capacitive loading incurs long delay time along the signal lines. At high frequencies, the delay time causes unacceptable performance. Another problem is the high power consumption caused by the output drivers. Since input/output (I/O) buffer power is directly related to the capacitive load, a high capacitive loading results in high power consumption. Lastly, the large capacitive loading limits the flexibility of running the signal traces on a printed circuit board.
Therefore there is a need in the technology to provide an efficient method and apparatus to interface a large memory array to a high-performance processor.